The present invention is generally directed to the management of instructions being processed in a high speed computer. More particularly, the invention relates to a system and method of use for interfacing a high speed processor to one or more I/O bus controllers for the asynchronous management of instructions written to I/O space.
The rapid evolution of processor technology in terms of clock rates and the number of instructions executed per clock cycle has created a computer architecture environment in which operations other than the execution of instructions by the central processor limit the execution rates of programs. An area of particular concern involves processor management of program defined input/output (I/O) instructions. The performance degradation caused by processor synchronized program I/O operations is particularly evident for contemporary processors having clock rates approaching or exceeding 100 Mhz given that clock synchronized I/O operations occur at I/O execution rates approximately an order of magnitude slower. The speed differential is typical for synchronized program load/store to I/O address space in that the conventional practice requires the central processor to wait until the I/O bus controller and related I/O device complete their operations. As a consequence, program I/O instructions have proven to be very undesirable for high speed computers.
Although new formulations of processor instructions which eliminate or minimize program I/O instructions are possible, there exist the overwhelming need to maintain compatibility with existing software which supports synchronous program I/O operations. Thus, it is important to have a hardware architecture which can directly execute the voluminous libraries of existing programs.
Given that program I/O "load" operations are normally followed by processor instructions which use the loaded data, namely the existence of strong dependency between the program I/O "load" instruction and the successive processing instructions, little benefit can be gained from the refined management of program I/O "load" instructions. In contrast, the present invention focuses on the improved management of I/O "store" operations to I/O space by using an interface between the central processor and I/O system.
An interface which manages program I/O store operations potentially provides significant processor efficiency improvements. However, the interface must be capable of running correctly with existing software and must provide a mechanism for managing error recover of I/O operations executing asynchronously to the processor.
Thus, there exists a need for a system architecture and method of operation by which a central or main processor can issue store instructions to I/O address space and not incur a stall as a consequence of the slow relative speed of the I/O system, yet retain full software compatibility and manage error recover.